ABSTRACT
The recent years have seen an exponential increase of devices per unit area. As the transistors’ size shrinks following Moore’s Law, the increased delay of wires began to outweigh the increased performance of small transistors. Decreasing the wire delay, e.g., by using the low-dielectric (low-κ) isolating materials releases the problem in 90 nm; but for 65 nm and beyond, an ultralow-κ material is required. Although this is technologically feasible, it may increase the fabrication costs [59]. Industry has been following the scaling dictate and technology innovation was pushed by the design requirements. Along with the miniaturization coming with new technology nodes, profound modifications to routing have been carried out. An increasing number of metal layers at ever smaller lithography pitch became necessary for the increasing number of devices to interconnect. In the last decade the scaling of the interconnect has slowed down due to technological barriers such as wire resistivity increase as well as high capacitive coupling between adjacent wires. All this requires more effort on the technological research side for less resistive materials and low-κ insulators with ever lower dielectric constant.
