ABSTRACT
This chapter focuses on static random access memory (SRAM) design using radiation hardening by design (RHBD) techniques. It focuses on both total ionizing dose (TID) and single event effect hardening. There are two basic approaches to fabricate radiation-tolerant integrated circuits—hardening by process and hardening by design. TID is mitigated by higher doping at the oxide interfaces or, when using RHBD approaches, by using annular or edgeless n-channel metal oxide semiconductor transistor gates. Easily the most common approach in hardened processes is the addition of resistors in the SRAM cell latch feedback path. In SRAM cells, RHBD using conventional techniques imposes a significant increase in size. To avoid a significant area impact for RHBD SRAMs, more clever TID mitigation techniques must be found. Reverse-body bias with and without simultaneous power supply collapse has been used in commercial integrated circuits for full-chip and memory standby power reduction.
