ABSTRACT
Traditional programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) allow circuit designers to implement logic circuits with fewer chips relative to standard gate level designs based on primitive gates and flip-flops. As a result, layout and unit production costs are generally reduced. In this chapter, we use the term ‘‘programmable device’’ to refer to the class of moderately complex singlechip devices, in which the user in the field can program the function of the device. We include
such devices as the programmable logic array (PLA), programmable array logic (PAL), programmable read-only memory (PROM), and the FPGA. Since most commercial vendors provide software design aids for mapping designs to their specific chips, initial design costs and time to market are low. Another important advantage of programmable device designs is ‘‘flexibility.’’ Design changes do not require physical changes to the printed circuit board as long as the revised functions still fit onto the same programmable chip. The low cost of design revisions makes programmable chips very attractive for prototype design and low volume production. Designers often move up the design ladder once proven designs move into high volume production. Table 9.1 shows the position of PLDs, PROMs, and FPGAs on the complexity ladder of device types. In the
‘‘range of realizable functions’’ column, we compare the range of realizations for various device types. Discrete gates can implement any function if enough gates are available. MSI chips implement very specialized functions such as shift registers, multiplexers (MUXs), decoders, etc. Table 9.1 compares programmable devices (PLDs, FPGAs, and PROMs) relative to the range of functions that can be implemented on a single chip. A PROMchipwith n address inputs can implement any combinational function ofn variables. A PLD chip with n inputs can implement only a subset of the combinational functions of n variables. Gate arrays can implement a wide range of both combinational and sequential functions. The programmable devices are characterized by low time to market, low design cost, low cost of modifications, and moderate production costs. Nonfield programmable devices such as mask programmable gate arrays (MPGAs), standard cell devices, and full custom devices are characterized by high initial design costs and longer time tomarket, but have lower volume production costs. Custom chips are preferred for large volume production because of the very low unit production costs. However, initial design costs and the cost of design changes are very high for custom chip design. Also, the design of custom chips requires highly trained personnel and a large investment in equipment. The low design cost, low cost of design changes, and low time tomarketmake PLDs and FPGAs good choices for lower volume production and for prototype development. The primary difference between PLDs and FPGAs arise because of a difference in the ratio of the
number of combinational logic (CL) gates to the number of flip-flops. PLD devices are better for applications that require complex CL functions that drive a relatively small number of flip-flops, such as finite-state machine (FSM) controllers or purely CL functions. FPGAs are better for devices that require arithmetic operations (adders, multipliers, and arithmetic logic units [ALUs]), or that require a large number of registers and less complex CL functions, such as digital filters.
