ABSTRACT
A superscalar processor is a computer designed to fetch, decode, and execute multiple instructions each clock cycle. The rationale for such a design can be illustrated by considering the basic computer performance equation, that is, execution time is a function of the path length (measured in number of instructions) multiplied by the cycles per instruction (CPI) multiplied by the clock cycle time. The goal of a pipelined processor is to strive towards a minimum CPI of 1.0, while simultaneously reducing or at least limiting any expansion of the path length or clock cycle time, and thus reduce the execution time. The goal of a superscalar design is to attain a fractional CPI, or, stated as the reciprocal, the goal is to attain instructions per cycle (IPC) greater than 1.0. With similar reductions or at least limits over the expansion of the path length and clock cycle time, the result is an even larger reduction in the execution time than for pipelining alone.
