ABSTRACT
The fixed-point number representation is appropriate for representing numbers with small numerical values that are considered as positive or negative integers; that is, the implied radix point is to the right of the low-order bit. The same algorithms for arithmetic operations can be employed if the implied radix point is to the immediate right of the sign bit, thus representing a signed fraction. Floating-point numbers consist of the following three fields: a sign bit, s; an exponent, e; and a fraction, f. Floating-point addition can be implemented with two fixed-point adders: one for fraction addition and one for exponent processing. The organization for floating-point addition can also be used for floating-point subtraction. The hardware assigned to the fractions must perform addition and also have the ability to shift the appropriate fraction right for fraction alignment. The Verilog Hardware Description Language design of a floating-point adder will be implemented using behavioral modeling for the single-precision format of 32 bits.
