ABSTRACT
Floating-point multiplication is slightly easier than addition or subtraction, because the exponents do not have to be compared and the fractions do not have to be aligned. For floating-point multiplication, the exponents are added and the fractions are multiplied. Both operations can be done in parallel. This chapter presents numerical examples using the sequential add-shift method with 8-bit operands. It designs two behavioral modules: one using the Verilog HDL multiplication operator, and one using the sequential add-shift method. This chapter describes the multiplication process is accomplished using any of the algorithms on fixed-point multiplication. It presents one of the Verilog HDL implementations uses the sequential add-uses the shift technique for floating-point multiplication. The multiplicand and multiplier are represented in sign-magnitude notation in either the single-precision format or the double-precision format. Multiplication using the single-precision format generates a double-precision 2n- bit product; therefore, the resulting fraction is 46 bits.
