Introduction to Verilog HDL

This chapter analyses the design of combinational and sequential logic using the Verilog hardware description language (HDL). An HDL is a method of designing digital hardware by means of software. A considerable saving of time can be realized when designing systems using an HDL. This offers a competitive advantage by reducing the time-to-market for a system. Verilog has a profuse set of built-in primitive gates that are used to model nets. The single output of each gate is declared as type wire. The inputs are declared as type wire or as type reg depending on whether they were generated by a structural or behavioral module. In addition to built-in primitives, Verilog provides the ability to design primitives according to user specifications. These are called user-defined primitives and are usually a higher-level logic function than built-in primitives. Gate-level modeling is an intuitive approach to digital design because it corresponds one-to-one with conventional digital logic design at the gate level.