ABSTRACT
Verification This chapter deals with verification, a group of methods and techniques used to detect design errors before a chip is created. This chapter describes the activities that are part of the verification process, including how to design testability into a chip and how to fully simulate a chip to ensure that it will function correctly in a completed system. The importance of and effort committed to verification is growing as CPLD and FPGA designs increase in size. In recent projects, I've found that more manpower is designated for verification than any other phase of the project. Also, all kinds of EDA tools are coming to the market to help with verification. Some of these tools are generic tools, and others are specifically for certain types of chips.
