ABSTRACT
Combinational Logic • Sequential Logic 3.5 Modeling a Three-State Gate 3-12 3.6 An Example 3-13 3.7 Behavioral Synthesis 3-17
Scheduling • ALU Allocation • Register Allocation 3.8 Conclusion 3-26
This chapter provides an overview of register transfer level synthesis and behavioral synthesis, contrasting the two with examples. Examples are written using VHDL and Verilog HDL, the two dominant hardware description languages (HDL) in the industry today.
