ABSTRACT
When logic networks are realized in transistor circuits on an integrated circuit chip, each gate in logic networks usually realizes more complex functions than AND or OR gates. But handy design methods are not available for designing logic networks with such complex gates under very diversified complex constraints such as delay time and layout rules. Thus, designers often design logic networks with AND, OR, and NOT gates as a starting point for design with more complex gates under complex constraints. AND, OR, and NOT gates are much easier for human minds to deal with. Logic networks with AND, OR, and NOT gates, are often converted into transistor circuits. This conversion process illustrated in Fig. 5.1 (the transistor circuit in this figure will be explained in later chapters) is called
technology mapping
. As can be seen, technology mapping is complex because logic gates and the corresponding transistor logic gates usually do not correspond one to one before and after technology mapping and layout has to be considered for speed and area
Also, logic gates are realized by different types of transistor circuits, depending on design objectives. They are called
logic families
. There are several logic families, such as ECL, nMOS circuits, static CMOS, and dynamic CMOS, as discussed in Chapters 8, 13, and 14. Technology mapping is different for different logic families.
