ABSTRACT
This chapter examines the fabrication processes required for transferring product designs to silicon (Si). In the field of process technology development, new lithography processes are needed that are capable of extending current optical lithography limits and pushing them beyond the optical spectrum. The chapter aims to present a simplified and logical flow for multilevel interconnect processing. Elegant interconnect schemes not only must make the interconnect system more reliable, but also be easy to etch and overcome the problems associated with the etch. The chapter focuses on the multilevel interconnect steps from dielectric deposition to metallization. There are several dielectric planarization processes currently being used for 1 μm and submicron process technologies. Contact process optimization and control are being scaled down and the number of contacts are increasing per unit area. Contact placement, size, metal overlap, and other design rule constraints make the management and control of the contact/via formation step very challenging.
