ABSTRACT
This chapter focuses on some detail at the implementation details of the Acorn RISC Machine, and the design methodologies which were used to produce it. The design of the ARM instruction set started with a decision to use a single instruction length of exactly one word, and the load/store model was adopted. The ARM instruction set has many features in common with other RISC instruction sets, for instance the load/store architecture. The design goal with ARM was to ensure that enough state is preserved inside the processor to make retrying any instruction which faults possible. The earliest design proposal for the ARM implemented load and store multiple with an address decrementer for modes which decrement from the base address. ARM is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred.
