ABSTRACT
This chapter focuses on some of the RISC research currently taking place which may indicate the way that architectures and organizations will continue to evolve to enable higher performance levels to be achieved. The introduction of RISC architectures has been accompanied by a very rapid rate of increase in available VLSI CPU power. The SPUR project at Berkeley is directed towards the construction of a multiprocessor system optimized for the execution of programs written in Common Lisp. It uses a novel address in-cache translation mechanism. The SPUR instructions represent a move away from the original RISC goal of a simple generic instruction set. The RISC approach has generated a phase of development where advances have come much faster than would have resulted from simply tracking improvements in processing. Loads and stores of single-, double- and extended-precision numbers Add, subtract, multiply, divide, compare, negate, absolute value Format conversion SPUR produces 32-bit virtual addresses.
