RF Communication Circuits

During the last decade of last century, the world of wireless communications started to grow rapidly. Today, cellular handsets are the largest consumer market in the world. The main trigger was the introduction of digital coding and digital signal processing in wireless communications. The aggressive scaling of CMOS process technology driven by the memory and microprocessor market made CMOS a logical choice for integration of digital signal processing in wireless applications. The development of these high performance, low-cost CMOS technologies allowed integration of enormous amount of digital functionality on one chip. This enabled the use of sophisticated modulation schemes, complex demodulation algorithms, and high-quality error detection and correction to produce high data rate communication channels bringing the Shannon limit in sight [1]. The radio frequency (RF) front-ends are the interface between the antenna and the digital modem of the

wireless transceiver. They have to detect very weak signals (mV) that come in at a very high frequency (10 GHz), and at the same time transmit high-power levels (up to several watts) at the same high frequencies. This requires high-performance analog circuits, like filters, amplifiers, and mixers that translate the incoming modulated data between the antenna and the A=D conversion and digital signal processing. Consumer electronicmarkets aremainly driven by low-cost and low-power consumption. This makes the RF front-ends the bottleneck for future wireless applications. Low-cost and low-power are both linked to high integration level. A high level of integration renders a significant space, cost, weight, and power reduction. A higher degree of integration requires less discrete components reducing the bill of materials cost. Keeping signals on chip greatly reduces power consumption since less I=O drivers are needed. Many

different techniques to obtain a higher degree of integration have been presented over the years [2-5]. This chapter introduces and analyzes some advantages and disadvantages and their fundamental limitations. Parallel to the trend for further integration, there is the trend to integrate RF circuitry in CMOS

technologies. While digital baseband processing has already been implemented in CMOS technology in several product generations, CMOS RF has only recently made its pace forward. For long time, many design houses believed complicated Mixed-Signal RF CMOS chips were impossible to realize. The main objective against CMOS RF was the lack of high-Q passive components and its poor noise performance. It took the persistence of some academic institutions and some pioneering firms to prove them wrong. It is clear that RF CMOS full potential would not have been unfold if only stand-alone radios were developed. CMOS RF systems on chip today implement all radio building blocks including phaselocked-loop (PLL), low-noise amplifier (LNA), power amplifier (PA), up-and down-conversion mixers, filters, and antenna switch. Furthermore, they include all digital baseband processing circuitry and ROM memory [6,7]. This reveals the real strength of CMOS RF over other ‘‘better-suited’’ technologies like Si Bipolar, BiCMOS, and Silicon Germanium (SiGe). Putting together RF and baseband in one chip permits compensation of lower radio performance with less expensive digital signal processing circuits, making its performance competitive with SiGe radios. Together with a possible 75% reduction of discrete components, RF CMOS offers the cheapest solution if one pursues the ultimate goal: A single chip including the physical layer (PHY) as well as the media access control (MAC) together with an MAC processor, memory, and I=O such as USBports or peripheral component interconnect (PCI) interfaces. RF CMOS is not a matter of just replacing bipolar transistors with their CMOS counterpart. It requires

a whole range a new architectures, techniques, and a high integration level. When compared with CMOS, SiGe requires less power for a certain gain and achieves a lower noise figure. The biggest drawback of CMOS is its inferior 1=f noise performance. This will only increase with the introduction of high-K dielectric materials in the gate of future CMOS technology nodes. CMOS design engineers therefore went looking for new topologies to reduce the impact of 1=f noise on the radio performance. Another problem that had to be overcome was the lack of high-Q passive components in CMOS technology. Extra processing steps as well as innovative layout and design techniques solved this problem. First, this chapter will analyze some concepts, trends, limitations, and problems posed by technology for high frequency design. Next we will discuss a variety of architectures used in modern RF CMOS transceivers. In the rest of the chapter, we will take a closer look at the different building blocks that appear in a typical RF transceiver. We will split this up between down-conversion, up-conversion, and frequency synthesis. In the final section, we will take a look at RF CMOS’s last barrier: RF power transmission. As CMOS gate

lengths shrink, lower voltages are tolerated at the transistor terminals. High-quality impedance converters must therefore be placed between the antenna and the transistor’s drain for high power transmissions. These are not available yet in integrated form. One of the major bottlenecks in CMOS PAs is combining high efficiency with high linearity. For high power transmission, designers are obliged to bias the PA high in its saturation region where linearity is low. Therefore, todays integrated PAs are limited to constant envelope modulation schemes likeGSM.High efficient PAs still remain out of reach formodulation schemeswith large peak-to-average power ratios like orthogonal frequency divisionmodulation (OFDM). This chapter discusses some circuit techniques to circumvent this bottleneck bringing the ultimate goal of a single-chip CMOS solution that is compatible with all standards and is capable of adapting itself a step closer to reality.