Figure 1.2 Transition of DRAM cells (excluding the 1T-1C cell). Here, we give a glimpse into a history of DRAM cells. The four-transistor
cell in flip-flop configuration was invented at almost the same time as the 1T-1C DRAM cell’s proposal, the equivalent circuit of which being shown in Fig. 1.2a.5 The cell develops large signal because it has a function of amplifying signal in itself. And all cells in an array can be refreshed simultaneously by raising word line (WL) with a pair of bit lines (BL and /BL) kept at a high voltage, increasing drastically the refresh efficiency with low retention power and busy rate. The three-transistor cell shown in Fig. 1.2b was then presented at a conference.6 This is the first commercialized cell in the i1103
1 kbit DRAM by Intel in 1970. Though it has an ability to draw current in itself,a refresh operation is required in which a sense amplifier circuit (S/A) reads the signal stored in a cell and restores the amplified data back to the cell before leakage current degrades the data too much to be detectable by S/A because it has no ability to refresh itself as the four-transistor cell has. The 1T-1C cell has been standard from 4 kbit generation. And it is possible to write complementary data into a pair of 1T-1C cells (two-transistor and two-capacitor) to enhance the signal amount, as is shown in Fig. 1.2c.