128 Mbit Floating Body RAM on Silicon-on-Insulator
To verify the extendibility of floating body cell (FBC) for embedded macros, a 128 Mbit floating body RAM (FBRAM) has been designed and fabricated. The memory cell design is based on 90 nm technology node. The operation of FBC has been designed as fully depleted MOSFET on silicon-on-insulator. Based on the measurement results of the 128 Mbit FBRAM, many kinds of important characteristics of FBC have been clarified. FBC has an adequate signal for the single cell operation. The data retention can be controlled by the electrical filed of the depletion layer, which is almost same as the conventional dynamic random access memory. As for the disturb issue, the effect of two kinds of disturb has been clarified. The one is bit line disturb, the other is bipolar disturb.