Cell Array Architecture and Sense Amplifier Design
Design of sense amplifier circuit (S/A) will be presented which is specific and appropriate to floating body RAM. At first, imperfection of nondestructivity for reading data from floating body cell (FBC) is discussed, and it is shown that placing a S/A for each bit line pair is necessary. Examples of S/A circuits for the twin cell and the single cell schemes are explained with special emphasis on dummy cell design for the latter scheme. Measurement results of memory chip functionality and retention time are analyzed to show optimum design of dummy cell systems. An open bit line cell array architecture for FBC which is immune against noise between bit lines is analyzed to show a big advantage over the one-transistor and one-capacitor dynamic random access memory cell.