ABSTRACT
Wafer-level three-dimensional (3D) integration offers the potential of enhanced performance and increased functionality, combined with the low manufacturing cost inherit from monolithic IC processing. This chapter addresses the problem of power delivery in microprocessors, applicationspecific ICs (ASICs) and system-on-a-chip (SoC) implementations, based upon a wafer-level 3D technology platform with arrays of monolithic DC-DC converter cells in one stratum providing power locally to the signal electronics strata. The chapter consists of five main sections: (1) a technical background of the increasing difficulty of delivering power to advanced ICs and the limitations of current technologies, (2) a brief review of 3D platforms that enable implementation of this power delivery architecture, (3) a description of the design of a prototype completely-monolithic, two-phase, point-of-load (PoL) buck converter cell, (4) a summary of the fabrication (using a 180 nm SiGe BiCMOS foundry process) and performance of the converter cell, and (5) a discussion of technologies and designs offering the promise of improved monolithic power converter performance. This power delivery architecture provides extreme power delivery flexibility, including dynamic control, at the expense of an additional stratum in a 3D chip stack. In addition, the power quality is controlled within the 3D chip stack, and the number of I/O power and ground pins is reduced. 3D Integration for VLSI Systems Edited by Chuan Seng Tan, Kuan-Neng Chen and Steven J. Koester Copyright © 2012 by Pan Stanford Publishing Pte. Ltd. www.panstanford.com
13.1 TECHNICAL BACKGROUNDPower delivery has become an important concern in the design of ICs, both as the power density of high performance microprocessors, ASICs and SoCs has increased with minimum feature size below 100 nm, and as the number of voltage levels increased to both minimize the total power dissipation of digital electronics and to optimize performance of mixed-signal functions. Conventional implementations incorporate DC-DC converters and/or voltage regulator modules (VRMs) near the high performance IC chips, with power delivery to the IC using multiple power and ground pins as depicted in Fig. 13.1. Power integrity is achieved by distributing decoupling capacitors in both the package and IC, resulting in a complex L-C-R network between the PoL converter (or VRM) and the signal electronics.
