ABSTRACT
Power and thermal issues have become the primary concerns in traditional 2D IC design. Although emerging 3D technology offers several benefits over 2D, the stacking of multiple active layers in 3D design leads to higher power densities than its 2D counterpart, exacerbating the thermal issue. Therefore, it is essential to conduct thermal-aware 3D IC designs. This chapter presents an overview of thermal modeling for 3D IC and outlines solution schemes to overcome the thermal challenges at Electrical Design Automation (EDA) and architectural levels. 14.1 INTRODUCTION3D technology offers several benefits compared to traditional 2D technology. Such benefits include: (1) The reduction in interconnect wire length, which results in improved performance and reduced power consumption; (2) Improved memory bandwidth, by stacking memory on microprocessor cores with TSV connections between the memory layer and the core layer; (3) The support for realization of heterogeneous integration, which could result in novel architecture designs; (4) Smaller form factor, which results in higher packing density and smaller footprint due to the addition of a third dimension to the conventional two dimensional layout, and potentially results in a lower cost design. However, one of the major concerns in the adoption of 3D technology is the increased power densities that can result from placing one power hungry block over another in the multi-layered 3D stack. Since the 3D Integration for VLSI Systems Edited by Chuan Seng Tan, Kuan-Neng Chen and Steven J. Koester Copyright © 2012 by Pan Stanford Publishing Pte. Ltd. www.panstanford.com
increasing power density and the resulting thermal impact are already major concerns in 2D ICs, the move to 3D ICs could accentuate the thermal problem due to increased power density, resulting in higher on-chip temperatures. High temperature has adverse impacts on circuit performance. The interconnect delay becomes slower while the driving strength of a transistor decreases with increasing temperature. Leakage power has an exponential dependence on the temperature and increasing on-chip temperature can even result in thermal runaways. In addition, at sufficiently high temperatures, many failure mechanisms, including electromigration (EM), stress migration (SM), time-dependent dielectric (gate oxide) breakdown (TDDB), and thermal cycling (TC), are significantly accelerated, which leads to an overall decrease in reliability. Consequently, it is very critical to model the thermal behaviors in 3D ICs and investigate possible solutions to mitigate thermal problems in order to fully take advantage of the benefits that 3D technologies offer.This chapter reviews recent efforts on thermal modeling for 3D ICs and outlines solution schemes to overcome the thermal challenges. We first focus on thermal modeling in Section 14.1.2. Then, in Section 14.1.3, we present several thermal-aware EDA solutions such as thermal-aware floorplanning, placement, and routing. Section 14.1.4 reviews several architecture solutions that help mitigate thermal impacts in 3D ICs. 14.2 THERMAL MODELING FOR 3D ICsThis section surveys several thermal modeling approaches for 3D ICs. A detailed 3D modeling method is first introduced, and then compact thermal models are introduced. An overview of a widely used architecture-level thermal tool, called HotSpot, and its 3D extension are described. Then a detailed 3D modeling is presented. 14.2.1 A detailed 3D thermal modelSapatnekar et al. proposed a detailed 3D thermal model.5 The heat equation (1), which is a parabolic partial differential equation (PDE) defines on-chip thermal behavior at the macroscale.
