ABSTRACT

Wafer bonding was first developed for the micro-electro-mechanical systems (MEMS) market, primarily as a wafer-level capping technique.5 The manufacturer would produce a MEMS wafer with some fragile structures (e.g., membranes and cantilever beams) and would then use another wafer to cap off and protect the MEMS structures, sealing off the cavities around them to ensure the functional environment and to prevent damage and contamination. Today wafer bonding is being used not only for capping MEMS wafers, but also for essentially stacking wafers with different functionalities for homogeneous and heterogeneous 3D integration.6-7 The industry can take various wafers (such as MEMS wafers, memory wafers, and CMOS processor wafers), stack them on each other, and then connect them by using TSV interconnects. Currently, a wide variety of wafer bonding methods are being used for various device packaging and engineered substrate manufacturing, which include molecular bonding, anodic bonding, metal bonding, glass frit

bonding and adhesive bonding depending upon whether an intermediate layer is used or not, as summarized in Figure 3.1.8

Fig. 3.1 Overview of different wafer bonding methods.However, many established bonding methods are not compatible with CMOS devices due to several issues. For instance, anodic, glass frit, Au-Au thermo-compression and some eutectic bonding methods are not considered due to the risk of metal ion contamination. The bonding temperature has to be compatible with the thermal budget of the devices, e.g., less than 400˚C for CMOS devices. The TSV diameter is limited due to space constraints, which requires the intermediate layer to be very thin in order to minimize the aspect ratio of the TSV. The bond layer needs very good thickness uniformity. Due to those issues, the bonding processes compatible with TSV-interconnected CMOS wafers are limited to such bonding methods as direct oxide bonding (SiO2), metal bonding (Cu-Cu or Cu-solder-Cu), adhesive bonding, and several hybrids of those methods as illustrated in Figure 3.2. 3D-IC stacking can be performed through chip-to-chip, chip-to-wafer or wafer-to-wafer approaches, each method having its own benefits and disadvantages. Chip-to-chip stacking is being used very broadly today, but is regarded as a very costly process for TSV applications. Wafer-to-wafer stacking is most practical for high yield devices. Chip-to-wafer stacking is believed to be best suited for low yield devices or heterogeneous stacking although pick-and-place, align, and bond assembly time is relatively costly when done chip-by-chip since there are no economics at the wafer level. If

any subsequent post-bond processing is required, surface planarity issues can create added processing complexity and cost compared to wafer-to-wafer alignment and bonding.