In 2012, DRAM technology reached the 30 nm technology node. Although many difficulties are encountered during device scaling, the mainstream DRAM technology is still based on the simple 1T1C (1 transistor-1 capacitor) configuration. Many innovations of manufacturing technologies and basic cell architecture are key enablers for DRAM’s further scaling [1-11]. The storage density of DRAM chip has increased from 16 Kb to 8 Gb and the feature size has been scaled from 2 μm down to 40 nm in the past 40 years. In this chapter, we will look into the major innovations of cell concepts and manufacturing technologies for realizing the nanoDRAM storage technology.