ABSTRACT
The flip-chip area-array package, which connects the active device side of the semiconductor face-down via solder bumps on a multi-layered substrate, has been identified as an enabling technology in the National Technology Roadmap for Semiconductors [1]. The development of flip-chip area-array packages in corporates new sets of materials, processes and interconnect structures, that are not always optimized or compatible because of specific functional requirements. Although the use of underfill encapsulation significantly improves the reliability of flip-chip solder interconnections, delamination at various interfaces becomes a major reliability concern for flip-chip packages, as reviewed by Wu et al [2]. Underfill delamination from the chip and/or the board is most commonly ob served and often leads to premature failure of the solder interconnects. These necessitate the assessment of interfacial adhesion reliability as part of design
and qualification of a plastic flip-chip package. However, emerging new materi als and processes, together with the demands for cost reduction and fast product cycles, present serious challenges to the assessment of interfacial adhesion reli ability.
