chapter  5
Peak-to-Average Power Ratio Implementation
Pages 44

One of the main factors to choose the peak-to-average power ratio (PAPR) technique is by verifying the feasibility of the PAPR technique and to ensure that the technique can be implemented in a test bed platform. There are few works that focus on the implementation of the PAPR technique. Most of the PAPR techniques that have been proposed until now suffer from feasibility. The main reason is the complexity of those techniques are mainly high. Today’s field programmable gate array (FPGA) technology has limited hardware resources. The main blocks in FPGAs are random access memory (RAM), multipliers, first input first output (FIFO), and adders. The most recent FPGAs are based on a system on chip (SOC) in which it has an Acorn RISC Machine (ARM) processor to integrate the C and VHSIC Hardware Description Language (VHDL). This is important in the sense that some PAPR techniques involved with computation within the iteration loop come from the feedback to optimize the PAPR value. Hence, in implemenation the processing needs to be done in an ARM processor. The conventional FPGAs had to microblaze or power the PC processor where the speed and size were less than the ARM processor. In the view of implementation where the hardware resource is the main concern and directly affects the system cost, the PAPR complexity is one of the main parameters used to evaluate the performance of it. But at the same time two other metrics, PAPR performance and bit error rate (BER), need to be considered. There is always a trade-off between these parameters. Some PAPR techniques enhance the PAPR performance, however, the complexity issue has not been considered. Some techniques have also not considered the complexity with respect to hardware resources. This is due to the fact that there is a distinction between computational complexity and hardware complexity. Thus, we have defined two metrics in order to

evaluate the complexity arising from the PAPR techniques: computational complexity reduction ratio (CCRR) and hardware complexity reduction ratio (HCRR). There is a major difference between these parameters. CCRR is mainly the complexity of the calculation in PAPR together with the number of multiplications and additions involved, especially in inverse fast Fourier transform (IFFT). However, the HCRR is a different value due to the fact that the number of multipliers in the feedback loop in the iteration only accounts for one time rather than the CCRR in which multipliers have to be counted for each iteration.