ABSTRACT
Thus for every junction capacitance and temperature, there is a maximum voltage gain. Figure 3(b) is a plot of the maximum gain. To determine the maximum gain, both the gate capacitance and the bias current of the SET were varied. The graph shows that it will be very difficult to make SET's with voltage gain greater than one that operate at room temperature. It will be even harder to get them to operate in a dense integrated circuit, which usually has a temperature of about 400 K. For room temperature voltage gain, the junction capacitance will have to be about 0.1 aF with a gate capacitance of 0.3 aF. This kind of SET has not yet been fabricated. So far, the largest voltage gain that has been observed is 5.2 and that was measured at 100 mK. [12] The highest temperature
Fig. 3(a) The voltage gain is plotted as a function of the gate capacitance and temperature for a junction capacitance of 0.1 aF. The voltage gain depends on the bias current. The bias current was adjusted to achieve maximum gain. The bias currents that were used were I= 1 nA at 4.2 K, I = 20 nA at 50 K, I= 50 nA at 100 K, I= 100 nA at 200 K, I= 200 nA at 300 K, I = 200 nA at 400 K, I = 300 nA at 500 K. (b) The maximum voltage gain possible for a given junction capacitance is plotted as a function of temperature. The currents which resulted in the maximum gain are given in the plot.
