ABSTRACT
The logic cell called CLB, as shown i n Figure 23, consists o f two 4 input look up tables, two flip-flops and the configuration circuitry. The cell is flexible and has a number o f configuration options including 5 input logic block, 32 x 1 or 16 x 2bit memory, and 16 x 1 dual por t memory. The high speed carry logic for ar i thmetic circuits is also available. Other resources on the chip i n clude tri-state buffers al lowing efficient bus oriented designs and wide decod ers making address decoding easier.
