ABSTRACT
With the prevalence of ultra-large-scale-integrated circuits (ULSICs), conventional wisdom about contamination control needs to be questioned and usual practices need to be reassessed. Profound change in the industry is impacting fundamental areas in process and equipment design, wafer handling, wafer environments, and metrology. In the past, much emphasis was placed on the cleanroom environment-state-of-the-art ULSI fabrica tion facilities are usually Class 1 or better. Further reduction in airborne contamination, especially particulate, is not appearing to be cost-effec tive. Today’s limiters of higher yields are the process equipment and the processes themselves where the probability of contaminating the wafer is much higher than from the Class 1 cleanroom environment. Every process step is a source of contamination and modem ULSI processes have well over 300 steps. *287
Integrated circuit manufacturing requires the extensive use of thin films of dielectric and conducting materials. These films are subsequently patterned using state-of-the-art lithography and etching techniques to realize the critical feature sizes for state-of-the-art CMOS, bipolar, and BiCMOS devices. Contamination control during processing is paramount to obtaining yielding devices in order to make device manufacturing eco nomical. This is especially true for very large scale (VLSI) and ultra large scale integrated circuits (ULSI).
