ABSTRACT
The fabrication of submicron microelectronic devices in semicon ducting crystals requires inducing a wide variety of physical and chemical processes. Epitaxy, oxidation, lithography, etching, ion implantation, and deposition all must be carried out with a high degree of process control and spatial uniformity. As device and feature sizes shrink below one micron, the inherent limitations of traditional furnace-based thermal processing methods become manifest. Foremost, we must reduce the total timetemperature cycling required to complete fabrication steps.M This reduc tion is motivated by the need to minimize thermal diffusion and its associ ated redistribution of as-implanted doping profiles, to reduce thermal defect creation and migration in the crystalline substrate, and to minimize ther mally-induced substrate warpage as required by submicron lithography.
