ABSTRACT
A newly developed video standard H.264/AVC provides significant better compression bit ratio and transmission efficiency [1][2]. To achieve these, much higher computation power is needed. The hybrid CPU/FPGA chip model contains CPU (DSP) and FPGAs can be used to reduce design cost and still support significant hardware customization. A H.264 Codec is implemented by a high end CPU (RM9000) and two FPGA implemented co-processors. This article presents a Table Look-Up Pipelined Multiplication-Accumulation Co-processor (MAC) for H.264 Codec, which can be Used for a large amount of computations in H.264 with one of the multiplicands is a constant. The proposed design is based on the table looking up to generate the partial products and a three-level pipelined architecture is presented. A high-speed implementation of MAC within Xilinx FPGA [4] is explored. Performance analysis shows that the proposed FPGA implemented MAC can achieve output rates beyond 1.53 Gbit/s.
