A Gbit-Scale Dram Stacked with ECR Mocvd SrTiO[sub(3)] Over rie Patterned u0[sub(2)]/TiN Storage Nodes

Abstract The capacitor requirements for Gbit-scale DRAMs are discussed in detail. The choice of SrTi0 3 thin films over a stacked Ru02/TiN structure for the 1 Gbit DRAM is explained, and particular emphasis is put on the necessity of a stacked capacitor structure and on the selection of a suitable electrode material. The influence of film composition, film thickness and substrate temperature on the properties of ECR MOCVD SrTi0 3 films is then presented. Maximum permittivity and low leakage current density were obtained for stoichiometric composition, Sr/Ti = 1.0. A thickness of at least 400 A was found to be necessary to obtain SrTi0 3 films with sufficient electrical properties. A substrate temperature of 450 °C was found to be a suitable temperature for direct deposition of crystallized SrTi0 3 and no degradation of the RuCtyTiN bottom electrode structure. A new reactive ion etching process was developed to pattern RuC>2 /TiN nodes. The key characteristics of this process are the use of an SOG mask, the choice of an O2 /CI2 gas mixture which allows reactive etching of Ru( > 2 at a high rate of 2500 A/min and with a RUO2 /SOG selectivity more than 10:1, and an O2 ashing treatment performed at 150 °C at the end of the etching process, which helps remove the damaged layer observed at the RuC> 2 surface after RuOyriN etching. A new stacked capacitor technology comprising reactive ion etching of Ru02/TiN storage nodes and low temperature deposition of SiTiC> 3 thin films by ECR MOCVD at 450 °C was successfully developed. A storage capacitance of 25 fF and a leakage current density of 8 x 10“7 A/cm2 can be obtained at half Vcc = + 1.0 V, for SrTi0 3 films with a sidewall thickness of 400 A deposited on 0.5 pm stacked Ru0 2 /TiN storage nodes. This capacitor technology is suitable for use in Gbit-scale DRAMs.