ABSTRACT
Surface cleaning techniques have been successfully used for integrated circuit (IC) manufacturing for more than 30 years. With shrinking dimensions of IC structures, the impact of particles on device yield becomes more and more impor tant. The critical particle size needs to be lowered proportionally to the technol ogy node. The concerns about the critical particle size measurements that are needed for sub-1 0 0 -nm technology have already been expressed on several occa sions, e.g., see the 2001 update International Technology Roadmap for Semicon ductors (ITRS). Consequently, smaller defects (such as nano-sized particles) need
to be monitored and removed. However, counting nano-sized particles deposited on substrates is a big challenge because the state-of-the-art light scattering in struments allow inspection of particles down to only 65 nm (KLA-Tencor SPl™) or 50 nm (SP1DLS) for wafers with extremely low surface roughness. In order to study particles smaller than 50 nm, an approach for quantifying the particle-count deposited on a substrate becomes necessary.
