ABSTRACT
The scaling of the SiO2 gate layer thickness in advanced generations of complementary metal–oxide–semiconductor (CMOS) processes is reaching its limits, both from the point of view of leakage current limitations as well as intrinsic reliability concerns (see the introductory chapter of this book). By using a thicker gate insulating layer with a higher dielectric constant than SiO2 (3.9), the leakage current flowing through the device is expected to decrease, and the reliability of the gate dielectric is expected to improve. Numerous recent works have indeed reported leakage current reductions in high-κ based MOS devices, as compared to SiO2 layers with equivalent electrical thicknesses [1–6]. However, defect generation in these materials under electrical stress, which is closely related to the reliability of the devices, has not yet been extensively studied. The purpose of this chapter is to discuss the generation of defects in MOS structures with very thin SiON/ZrO2 gate stacks. Defect build-up in these devices is investigated by monitoring the variations of the current density and the capacitance–voltage (C–V) characteristics of the structures during constant gate voltage stress experiments.
