ABSTRACT

Since 1994, the International Technology Roadmap for Semiconductors (ITRS) [1] (figure 5.2.1) has been accelerating the scaling of CMOS devices to lower dimensions continuously despite the difficulties that appear in device optimization. ITRS roadmap acceleration since 1994 [<xref ref-type="bibr" rid="ref5_2_1">1</xref>]. Example for MPU and ASIC products. https://s3-euw1-ap-pe-df-pch-content-public-p.s3.eu-west-1.amazonaws.com/9780429092886/30cece93-10cf-4fa6-819c-64288338b87a/content/fig5_2_1.tif"/>