ABSTRACT

It is not an overstatement that the realization of the semiconductor era, better known as, the ‘silicon age’, owes much to the simple fact that silicon has a native insulator, SiO2, of superb quality. In this epic, relentless scaling, much more than diversification, was, and still appears as, a natural law, propelling dazzling progress and leading to fascinating technological achievements. The benefits include the fact that the more an integrated circuit (IC) is scaled, the higher becomes its packing density and circuit speed, and the lower its power consumption. Progress in Si IC technology projects scaling from the current 0.18–0.25 μm minimum lithographic line width devices towards the next 0.1 μm generation, implying that the current SiO2 gate dielectric must scale below 2nm thickness [1].