ABSTRACT
With continued process technology scaling, wire delay and design complexity has imposed significant constraints on traditional, superscalar proces-
Era
sor design [6]. Achieving high performance in superscalar processors requires complex, dynamic operand bypass networks to route the output of producer instructions to the input of consumer instructions in a timely fashion. Traditionally, operand bypass networks in superscalar processors were implemented with ad-hoc buses and point-to-point networks; however, as smaller process technologies led to greater numbers of instructions in flight and increased wire delays, the unfeasibility of building a traditional, ad-hoc point-to-point operand network has limited the scalability of superscalar processors. This chapter describes the design and implementation of a scalable, Network-onChip (NoC) based, operand bypass network as an alternative to traditional operand bypass networks.
