ABSTRACT
Coarse-grained reconfigurable architectures are considered appropriate for embedded systems because they can satisfy both flexibility and high performance requirements. However, power consumption is also crucial for the reconfigurable architecture to be used as a competitive processing core in embedded systems. In this chapter, we describe an efficient power-conscious architectural technique called reusable context pipelining (RCP) [43] to reduce power consumption in configuration cache. RCP is a universal approach in reducing power and enhancing performance for CGRA because it can be achieved by closing the power-performance gap between low-power-oriented spatial mapping and high performance-oriented temporal mapping. In addition, hybrid configuration cache structure is more efficient than previous one in terms of memory size.
