ABSTRACT
Most of the coarse-grained reconfigurable array architectures (CGRAs) are composed of reconfigurable ALU arrays and configuration cache (or context memory) to achieve high performance and flexibility. Specially, configuration cache is the main component in CGRA that provides distinct feature for dynamic reconfiguration in every cycle. However, frequent memory-read operations for dynamic reconfiguration cause much power consumption. Thus, reducing power in configuration cache has become critical for CGRA to be more competitive and reliable for its use in embedded systems. In this chapter, we address the power reduction issues in CGRA and provide a framework to achieve this. A design flow and a configuration cache structure are presented to reduce power consumption in configuration cache [41]. The power saving is achieved by dynamic context compression in the configuration cache-only required bits of the context words are set to enable and the redundant bits are set to disable. Therefore, the efficient design flow for CGRA has been proposed to generate architecture specifications that are required for supporting dynamically compressible context architecture without performance degradation. Experimental results show that the proposed approach saves up to 39.72% power in configuration cache with negligible area overhead (2.16%).
