ABSTRACT
Coarse-grained reconfigurable architecture (CGRA) based embedded system aims at achieving high system performance with sufficient flexibility to map variety of applications. However, significant area and power consumption in the arrays prohibits its competitive advantage to be used as a processing core. In this chapter, we present a computing hierarchy consisting of two reconfigurable computing blocks with two types of communication structure together [45]. In addition, the two computing blocks have shared critical resources. Such a sharing structure provides efficient communication interface between them with reducing overall area. Based on the proposed architecture, optimized computing flows have been implemented according to the varying applications for low power and high performance. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.
