ABSTRACT
Figure 3.1 shows the general relationship between performance and flexibility for different kinds of IP-types for embedded systems. The more flexible a IP is, the lower performance it has. Therefore, a traditional hardwaresoftware codesign flow maps applications into application-specific integrated circuit (ASIC) or general purpose processor (GPP). Performance-critical parts in an application software are mapped to ASIC and the rest of the application is mapped to GPP. Such a codesign flow enables the embedded systems to be optimized for the specific applications. However, the embedded applications rapidly change by consumers’ need and it means the embedded systems should be re-fabricated according to the changed applications in order to meet contraints on performance and power. Therefore, such a traditional codesign method exposes its limitation in the aspect of flexibility.
