ABSTRACT
This chapter discusses the impact and optimization of placement on the routing stage. This is commonly referred as congestion-driven placement. Congestion-driven placement techniques can be classified into the following groups: netlist connectivity-based methods, pin-density-based methods, and routing-estimation-based methods. In physical design, the required routing resources are captured in terms of routing congestion. Addressing the concerns improves the overall quality of the physical design in terms of performance of the circuit, wirelength, power consumed, congestion owing to global nets. The work targets the technology-independent logic optimization stage. Several of the popular congestion mitigation techniques can be classified as a priori congestion techniques, online methods, and posteriori methods. The advantage is on the fidelity side—congestion improvement achieved in placement can be mostly carried on to the routing. The target whitespace map is derived from the initial congestion map. As circuit sizes increase, simulated annealing is no longer a good choice as an global-placement algorithm because of its weak scalability.
