ABSTRACT
This chapter introduces several effective techniques of wire sizing. Because the interconnect delay depends on the wire width, length, and the buffer sizes and placement, optimally sizing the wires and buffers can help in minimizing the interconnect delay as well as power consumption. The wire over the substrate can be modeled as a conductor over the ground plane. Wire-sizing optimization tries to determine the optimal wire widths for each wire segment in an interconnect tree to minimize an objective function, which may be the interconnect delay, power, or a combination of both. Wire-sizing optimization may be continuous or discrete. Similar to the wire-sizing problem, the simultaneous gate and wire-sizing problem can also be formulated as a convex optimization problem as the gate delay can be modeled as a posynomial function as well. Nonuniform wire sizing is not used widely because routing such wires is nontrivial, and it can also lead to poor track utilization.
