ABSTRACT
This chapter discusses IBM’s physical synthesis tool, called placement-driven synthesis or placement-driven synthesis. It presents a description of the basics of the tool and some innovations in turnaround time published. The chapter focuses on physical synthesis in the context of a typical flat Application specific integrated circuit design style. Besides basic timing closure, there are many newer challenges that the physical synthesis system needs to handle. Optimization of critical paths is at the heart of any physical synthesis system. The most effective optimizations are generally buffering and gate sizing. The descriptions of some of the above incremental synthesis optimizations are deceptively simple. Engineers have been employing hierarchical design since the advent of the hardware description languages. In general, power gating can be physically implemented in the designs using block-based coarsegrained power gating and intrablock fine power gating.
