ABSTRACT
This chapter provides some necessary preliminaries with respect to the floorplan design problem. It presents several schemes for representing slicing floorplans and several important optimization problems, including the well-known area optimization problem, and their solutions for slicing floorplans. The chapter focuses on classical slicing floorplan design, and introduce different solutions and modern slicing floorplan design that takes placement constraints into account. It addresses several placement constraints and describes their solutions. The chapter highlights more advances in slicing floorplan design for field programmable gate arrays and three-dimensional integrated circuits, in addition to several interesting theoretical results. The hierarchical structure of a slicing floorplan can be described by an oriented rooted binary tree, calledslicingtree. On the basis of the floorplan topology, various optimization problems are then solved to minimize a given cost measure. The point-configuration based approach treats each module as a point by ignoring the area of the module.
