ABSTRACT
With the increasing demand of high-quality video on handheld devices, we will see widespread use of the state-of-the-art video compression standard H.264 Advanced Video Coding (H.264/AVC) in cell phones, PDAs, and smart phones in the next few years. Currently, complicated H.264/AVC decoding requires very high processor frequency to meet the real-time requirement, consuming an unacceptable amount of power. Therefore, a low-power implementation is needed. In this chapter, we describe a pure hardwired H.264/AVC main profile video decoder that has been implemented in Verilog RTL, equipped with an AMBA bus interface, and demonstrated in an FPGA prototype.
We present our development process, the SOC platform used, and its associated design methodology as well as lessons learned. Our decoder takes as its input H.264/AVC compressed video bit stream and produces as its output video frames ready for display. We wrap the decoder core with an AMBA-AHB bus interface and integrate it into a multimedia SOC platform. Several architectural innovations such as massive parallelism and data reuse at both IP and system levels are proposed to achieve high performance at a low operating frequency. Running at a 16 MHz FPGA, our decoder can real-time decode D1 video (720 × 480) at 16 frames per second, providing an over 20 times performance improvement over todays mainstream DSP approach. With its low-operating-frequency requirements and thorough consideration of system-level overhead, this H.264/AVC decoding system can significantly improve the power consumption and video quality of real-time mobile video applications.
