ABSTRACT
A reconfigurable mesh is a processor array that consists of processors arranged in a one-or two-dimensional grid with a reconfigurable bus system (Figure 15.1). The reconfigurable mesh of size m × n consists of mn processors arranged in a two-dimensional grid. For later reference, let PE(i, j) (0 ≤ i ≤ m − 1 and 0 ≤ j ≤ n − 1) denote a processor at position (i, j). Also, one-dimensional reconfigurable mesh of size m is the reconfigurable mesh with a single row. Similarly, let PE(j) (0 ≤ j ≤ m − 1) denote a processor at position j . The control mechanism of the reconfigurable mesh is based on the SIMD principle. A single control unit dispatches instructions to each processor. Although all processors execute the same instructions, their behaviors may differ, because they work on different input and different coordinates. On the reconfigurable mesh, any two adjacent processors are connected with a single fixed link.
