ABSTRACT
To close the processor-memory speed gap, the memory system of Multiprocessor System-on-Chip (MPSoC) is always organized as a two-level memory hierarchy: on-chip and off-chip memory. On-chip memory can be directly accessed by processors with very low latency, whereas the access latency of off-chip memory is much higher. In modern embedded processors, Scratch Pad Memory (SPM) is increasingly being employed due to its inherent advantages in terms of chip size, energy-efficiency, and timing predictability compared to cache. SPM consists of an SRAM array and decoders, which can be easily integrated into the chip. The main difference between SPM and cache is that the SPM guarantees a single-cycle access time, whereas an access to the cache is subject to cache miss which may take thousands of cycles. Data storage onto the SPM is not automatically controlled by hardware. Therefore, a scratch pad memory has 34% smaller area and 40% lower power consumption than a cache memory of the same capacity [18]. Commercial embedded processors, such as Motorola MCore [3], Texas Instruments TMS370Cx [4], Motorola 68HC12 [1], etc., take SPM as their on-chip memory.
