Evaluation of important reliability parameters using VHDL-RTL modelling and information flow approach

Using the stack processor emulator and benchmarks, an emulation model for fault injection was developed to estimate the dependability of the complex programmable system in operational phase. Through the fault injection into the emulator, the software fault tolerance effect on system is evaluated in this work. This effect is measured by the flow informational modeling approach. The faults consist of the single bit-flip, hardware fault (failure of component) and stuck-at-value faults in the internal registers of the stack processor and in memory cells.