ABSTRACT
The most critical task in designing a modern integrated circuit is to select a set of circuit parameters, such that the overall performances of the circuit meet the design specifications. Due to the extremely high nonrecurring engineering cost for fabricating prototype circuits, the conventional bread-board based circuit design method is no longer a feasible solution. The high complexity of the Very Large Scale Integration (VLSI) circuit also prohibits the explicit formulation of an analytical model of the entire circuit. Instead, the only viable alternative is to perform extensive circuit simulations. Existing circuit simulators, such as SPICE [1] and ASTAP [2, 3], have been widely used for such purposes. With the development of better models of individual devices, these circuit simulators are able to accurately predict the circuit responses based on the given set of design parameters. However, as the size of today's circuits increases dramatically, the computation cost, in terms of computing time and computing resources, for each
simulation run grows accordingly. Hence, it is highly desirable to restrict the total number of simulation runs required for circuit design optimization.
