ABSTRACT
CONTENTS 1.1 Introduction ............................................................................................................................ 1 1.2 Shallow Junction Processing Primer ................................................................................... 2 1.3 Implant Process: Nuclear and Electronic Stopping .......................................................... 2 1.4 Annealing................................................................................................................................ 3 1.5 Defect Evolutionary Processes ............................................................................................. 5
1.5.1 Submicroscopic Defects.............................................................................................. 6 1.5.2 Dot Defects................................................................................................................... 8 1.5.3 311 Defects ................................................................................................................... 8 1.5.4 Loops .......................................................................................................................... 12
1.6 Defects in Ultra-Shallow Processes ................................................................................... 13 1.6.1 Surface Effects............................................................................................................ 13 1.6.2 Millisecond Annealing ............................................................................................. 14 1.6.3 Regrowth-Related Defects ....................................................................................... 20
1.7 Conclusions........................................................................................................................... 22 References...................................................................................................................................... 23
The widely quoted International Technology Roadmap for Semiconductors (ITRS) [1] enumerates critical device dimensions (physical gate lengths, oxide thickness, junction depths, etc.) needed to meet performance goals of the future. The ITRS bases its predictions on a scaled planar silicon technology, and is an invaluable aid for defining process tool capabilities and providing a sense of scale for modeling efforts needed in the near future. Many of the techniques and structures for these devices are not yet known and much of the roadmap has been coded ‘‘research required.’’ The device at the far end of the road might be a traditional bulk device [2], a dual gate silicon-on-insulator (SOI) device [3], a ‘‘FinFET’’ [4], or even a vertical device [5]. The shallow junction specification of the roadmap is quite daunting. High conductivity,
extremely shallow junctions have to be formed. It is likely that future devices will have metastable dopant concentrations in the source and drain to attempt to control parasitic elements. Lattice defects have an enormous impact on the final electrical characteristics of the junction. As we will see, damage from implantation controls the junction depth and
understanding the electrical properties of doped layers in silicon.
