ABSTRACT
CONTENTS 5.1 Introduction ........................................................................................................................ 120 5.2 Oxide Defects ..................................................................................................................... 120
5.2.1 Fixed Oxide Charge................................................................................................ 120 5.2.2 Mobile Oxide Charge ............................................................................................. 121 5.2.3 Oxide-Trapped Charge .......................................................................................... 121 5.2.4 E0 Center ................................................................................................................... 122 5.2.5 Neutral Electron Traps........................................................................................... 122 5.2.6 Interface-Trapped Charge...................................................................................... 124 5.2.7 Border Traps ............................................................................................................ 125 5.2.8 Interface between Two Different Insulators ....................................................... 127
5.3 Measurements .................................................................................................................... 128 5.3.1 Capacitance-Voltage .............................................................................................. 128
5.3.1.1 Theory ......................................................................................................... 128 5.3.1.2 Interface Traps ........................................................................................... 132 5.3.1.3 Border Traps............................................................................................... 134
5.3.2 Conductance ............................................................................................................ 135 5.3.2.1 Interface Traps ........................................................................................... 135 5.3.2.2 Border Traps............................................................................................... 136
5.3.3 Bias-Temperature Stress......................................................................................... 137 5.3.4 Triangular Voltage Sweep ..................................................................................... 137 5.3.5 Deep-Level Transient Spectroscopy ..................................................................... 138
5.3.5.1 Bulk Traps .................................................................................................. 138 5.3.5.2 Interface Traps ........................................................................................... 139 5.3.5.3 Border Traps............................................................................................... 140
5.3.6 Charge Pumping ..................................................................................................... 141 5.3.6.1 Interface Traps ........................................................................................... 141 5.3.6.2 Border Traps............................................................................................... 144
5.3.7 MOSFET Subthreshold Slope................................................................................ 146 5.3.7.1 Interface Traps ........................................................................................... 146 5.3.7.2 Oxide Traps ................................................................................................ 147 5.3.7.3 Border Traps............................................................................................... 148
5.3.9 Stress-Induced Leakage Current......................................................................... 149 5.3.10 Substrate Hot Electron Injection ......................................................................... 151 5.3.11 Constant Gate Voltage Oxide Stress .................................................................. 152 5.3.12 1=f Noise................................................................................................................. 152 5.3.13 Electron Spin Resonance...................................................................................... 154
5.4 Summary............................................................................................................................. 157 References.................................................................................................................................... 158
Defects in gate oxides and insulators have been characterized by many techniques, e.g., electrical, electron beam, ion beam, x-rays, neutron activation analysis, electron spin resonance, and others. These methods played a crucial role during the early metal-oxide semiconductor (MOS) development to determine the origin of oxide and interface charges that led to unstable MOS devices. Thermally grown oxides on silicon are now quite well understood and very well controlled during manufacturing. High-K dielectrics, however, have proven to be less well controlled and more difficult to characterize. This chapter gives a brief description of the common defects (oxide, border, and interface traps) and then describes many of the more common electrical characterization techniques used to estimate their densities and=or energy levels.
