ABSTRACT
There are many variations in the pixel design layout. First, the designer must choose whether the a-Si:H TFTs will be configured as back-channel-etched TFTs or channel-passivated TFTs (see Section 3.1). Next, the TFT layout and the pixel electrode design must be consid
Figure 2.8 Two examples of pixel layouts: a) the additional capacitance type, Cadd, and b) the storage capacitance type, Cst. These designs are not drawn to scale.
